Method of operating non-volatile memory

ABSTRACT

A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of Ser. No. 11/248,698, filed on Oct. 11, 2005, now pending. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of operating a memory device. More particularly, the present invention relates to a method of operating a non-volatile memory.

2. Description of the Related Art

Electrically erasable programmable read only memory (EEPROM) is one type of non-volatile memory that permits multiple data input, readout and erasure. Furthermore, input data can still be retained after power supply to the device is removed. Therefore, EEPROM has become one of the mostly widely adopted memory devices for personal computer and electronic equipment.

Typically, each EEPROM cell has a floating gate and a control gate fabricated using doped polysilicon. In the process of programming the memory cell, electrons injected into the floating gate will distribute evenly over the entire polysilicon floating gate layer. However, if the tunneling oxide layer underneath the polysilicon floating gate has some defects, current may leak out from the device causing reliability problems.

To minimize the current leak in the EEPROM device, a conventional method includes replacing the polysilicon floating gate with a charge-trapping layer. The charge-trapping layer is fabricated using silicon nitride, for example. The silicon nitride charge-trapping layer is normally sandwiched between a top silicon oxide layer and a bottom silicon oxide layer to form a stacked gate structure comprising an oxide/nitride/oxide (ONO) composite dielectric layer. An EEPROM having such as stacked gate structure is frequently referred to as a nitride read-only-memory (NROM).

Since the NROM is normally programmed through the injection of hot electrons, a high operating voltage and a high power rating is required. However, as the size of non-volatile memory cells continues to shrink due to miniaturization, the length of the channel must be reduced. Therefore, a high operating voltage will intensify the punch-through effect and result in a higher leakage current and a lower programming efficiency.

SUMMARY OF THE INVENTION

Accordingly, at least one objective of the present invention is to provide a method of operating a non-volatile memory capable of increasing programming efficiency.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of operating a non-volatile memory. The non-volatile memory comprises a gate over a substrate, a charge-trapping layer between the gate and the substrate, a source region in the substrate on one side of the gate and a drain region in the substrate on another side of the gate. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. The threshold voltage of auxiliary charge region is about 4 to 5V and the threshold voltage of data storage region is about 2V. There is an abrupt electrical field between auxiliary charge region and data storage region. Therefore the programming efficiency of the memory is enhanced. Furthermore, electrons have been injected into the auxiliary charge region before prosecuting the operation. To prosecute a programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is bigger than the fourth voltage, the third voltage is bigger than the second voltage, and the second voltage is bigger than the fourth voltage to initiate a channel initiated secondary hot electron injection (CHISEL) to inject electrons into the data storage region.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the first voltage is between about 2 to 7V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the first voltage is between about 4 to 5V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the second voltage is between about −2 to 2V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the second voltage is about 0V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the third voltage is between about 3 to 6V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the third voltage is between about 4 to 5V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the fourth voltage is between about 0 to −4V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the fourth voltage is between about −1 to −2V.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the charge-trapping layer is fabricated using silicon nitride.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the charge-trapping layer includes a composite film layer comprising an insulating layer and a nanometer crystal layer embedded within the insulating layer.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the non-volatile memory further includes a first dielectric layer disposed between the substrate and the charge-trapping layer.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the material constituting the first dielectric layer includes silicon oxide.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the non-volatile memory further includes a second dielectric layer disposed between the charge-trapping layer and the gate.

According to the aforementioned method of operating the non-volatile memory in one preferred embodiment of the present invention, the material constituting the second dielectric layer includes silicon oxide.

In the operating method of the present invention, channel initiated secondary hot electron injection is used to perform a programming operation so that the programming voltage and the programming current can be reduced. It also has the abrupt electric field between auxiliary charge region and data storage region. A higher programming efficiency is obtained because of the CHISEL program method and the abrupt electrical field.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic cross-sectional view of a non-volatile memory according to one embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic cross-sectional view of a non-volatile memory according to one embodiment of the present invention. As shown in FIG. 1, the non-volatile memory cell comprises a substrate 100, a gate 102, a charge-trapping layer 104, a source region 106 and a drain region 108. The substrate 100 is a P-type silicon substrate, for example.

The gate 102 is disposed on the substrate 100. The gate 102 is fabricated using doped polysilicon, for example.

The charge-trapping layer 104 is disposed between the gate 102 and the substrate 100. The charge-trapping layer 104 is fabricated using silicon nitride, for example. In addition, the charge-trapping layer 104 can be a composite film layer comprising an insulating layer and a nanometer crystal layer embedded within the insulating layer. The charge-trapping layer 104 close to the source region 106 is an auxiliary charge region 104 a while the charge-trapping layer 104 close to the drain region 108 is a data storage region 104 b.

The source region 106 is disposed in the substrate 100 on one side of the gate 102 and the drain region 108 is disposed in the substrate 100 on another side of the gate 102. The source region 106 and the drain region 108 are n-doped regions, for example.

In addition, a dielectric layer 110 may be disposed between the substrate 100 and the charge-trapping layer 104 and another dielectric layer 112 may be disposed between the charge-trapping layer 104 and the gate 102. The dielectric layer 110 and the dielectric layer 112 are fabricated using silicon oxide, for example.

In the method of operating a non-volatile memory according to the present invention, electrons are injected into the auxiliary charge region 104 a before proceeding with the programming operation. The method of injecting electrons into the auxiliary charge region 104 a includes performing a channel hot electron injection, for example. Hence, in an actual programming operation, the voltage applied to the gate 102 will be subjected to the shielding effect by the charges within the auxiliary charge region 104 a. As a result, the substrate 100 under the gate 102 can have an abrupt electrical field between auxiliary charge region 104 a and data storage region 104 b that facilitates the injection of electrons into the data storage region 104 b of the charge-trapping layer 104.

To program the non-volatile memory of the present invention, a first voltage is applied to the gate 102, a second voltage is applied to the source 106, a third voltage is applied to the drain region 108 and a fourth voltage is applied to the substrate 100. The first voltage is bigger than the fourth voltage, the third voltage is bigger than the second voltage and the second voltage is bigger than the fourth voltage to initiate a channel initiated secondary hot electron injection (CHISEL). As a result, electrons are injected into the data storage region 104 b of the charge-trapping layer 104. The range of first voltage is about 2 to 7V, for example, better performance is about 4 to 5V. The range of second voltage is about −2 to 2V, for example, better performance is about 0V. The range of third voltage is about 3 to ˜6V, for example, better performance is about 4 to 5V. The range of fourth voltage is about 0 to −4V, for example, better performance is about −1 to −2V.

In the aforementioned programming operation, the channel hot electrons generated from the source region 106 will produce electron-hole piles in the substrate 100 through bombardment. Because the fourth voltage applied to the substrate 100 is smaller than the first voltage applied to the gate 102, the electric field thus produced will drive the holes to flow in the direction of the electrode potential set up in the substrate 100. Consequently, more electron-hole piles are created through bombardments. The secondary electrons created through the bombardments, subjected to the influence of the electric field, will inject into the charge storage region 104 b of the charge-trapping layer 104. Since the present invention utilizes channel initiated secondary hot electron injection effect to perform the programming operation, and the memory cell also has abrupt electrical field between auxiliary charge region, the programming voltage and current can be reduced significantly and the programming efficiency is increased.

In summary, the major advantages of the present invention at least includes:

1. The method of programming the non-volatile memory according to the present invention can reduce programming voltage and programming current, so that a higher programming efficiency is obtained.

2. In the method of operating the non-volatile memory of the present invention, electrons have been injected into the auxiliary charge region prior to performing the programming operation. Hence, an abrupt electric field is set up within the substrate to facilitate the injection of electrons into the charge storage region and improve programming efficiency.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents. 

1. A method of operating a semiconductor device comprising a gate and a substrate, a charge storage element disposed between the gate and the substrate, a source region and a drain region disposed in the substrate, wherein the charge storage element comprises a non-data auxiliary charge region and a data storage region, wherein the non-data auxiliary charge region is filled with a predetermined amount of charges, the operating method comprising: providing a first voltage to the gate and a second voltage to the substrate to generate a first electric field; and providing a third voltage to the source region, and a fourth voltage to the drain region to generate a second electrical field, wherein the first and the second electrical fields drive a plurality of charges to the data storage region.
 2. The method of claim 1, wherein the first voltage is greater than the second voltage.
 3. The method of claim 1, wherein the fourth voltage is greater than the third voltage.
 4. The method of claim 1, wherein the third voltage is greater than the second voltage.
 5. The method of claim 1, wherein the first voltage is between about 2 to 7 volts.
 6. The method of claim 1, wherein the first voltage is between about 4 to 5 volts.
 7. The method of claim 1, wherein the second voltage is between about 0 to −4 volts.
 8. The method of claim 1, wherein the second voltage is between about −1 to −2 volts.
 9. The method of claim 1, wherein the third voltage is between about −2 to 2 volts.
 10. The method of claim 1, wherein the third voltage is about 0 volt.
 11. The method of claim 1, wherein the fourth voltage is between about 3 to 6 volts.
 12. The method of claim 1, wherein the fourth voltage is between about 4 to 5 volts.
 13. A semiconductor device, comprising: a gate configured on a substrate; a source region and a drain region disposed in the substrate; and a charge storage element disposed between the gate and the substrate, wherein the charge storage element comprises a non-data auxiliary charge region and a data storage region, and the non-data auxiliary charge region is filled with a predetermined amount of charges.
 14. The semiconductor device of claim 13, wherein a material constituting the charge storage element includes silicon nitride.
 15. The semiconductor device of claim 13, wherein the charge storage element further includes a composite film layer comprising an insulating layer and a nanometer crystal layer embedded within the insulating layer.
 16. The semiconductor device of claim 13, wherein the non-volatile memory further includes a first dielectric layer disposed between the substrate and the charge storage element.
 17. The semiconductor device method of claim 16, wherein a material constituting the first dielectric layer includes silicon oxide.
 18. The semiconductor device method of claim 13, wherein the semiconductor device further includes a second dielectric layer disposed between the charge storage element and the gate.
 19. The semiconductor device of claim 18, wherein a material constituting the second dielectric layer includes silicon oxide. 